RF HF router

I2C controlled HF RF router for HF+50 MHz

4L controlled impedance PCB

Contains :

• DC blocking, ESD protection, overvoltage protection,
• NYQ filter, 
• low noise linear voltage regulator for step-ATT
• switchable 0.5dB-step-ATT, 
• switchable HPF, 
• switchable 20 dB preamplifier 
• switchable RF-ports for external BPF module and for direct RF signal routing to ADC.

XtremeDx H7113R Transceiver assembly

 The front panel and PCB for XtremeDx H7113R SDR

(not real scale)

    

4L PCB, The bottom layer

Top view, all layers

STM32 controller. Diff RF decoupled from 12VDC power supply. 7 ADC multiplexed inputs for DC U/I measurements as RFDSP voltage and current, PA voltage and current, VSWR voltages on VSWR bridge). Hole for one optical encoder. Holes for two mechanical rotary encoders - MULTI and ATT, one analog potentiometer for volume control on ADC. All inputs are RF and ESD protected. USART for communication with baseboard. (this architecture was tested in my H7R SDR) 

Front panel and PCB assembly

 

The front panel + the display

    

2024.09.dd

   2026.02 

202607

HF PA100 F101 2V0

 HF PA100 F101 2V0

HF power amplifier 3.5...50 MHz

- output power: 120W..150W PEP from 50 MHz down to 3.5 MHz (150W PEP on 14.2 MHz) 

- with driver section

- input power: 0..3 dBm

- min 30 dB PEP IMD3, max 36...38 dB PEP IMD3 

2026.07 - 2V0

Two element delta-loop antenna for 20m band

Two element critical coupled delta-loop antenna for 20m band. 

The distance between elements is 3m. One element is radiator the another is the reflector. The radiation direction can be changed using relay.

The F/B ratio is 26..30 dB. The SWR is 1.2- 1.4.

QRO - Linear Power Tube Amplifier - 800W PEP CW/SSB

 2x GI7B tubes.

Husky world

 Husky world

XtremeDX HF SDR

- 2x 16b A/D (LTC2208) - 0...60 MHz RF (fNyq) input 

            - LVDS connection

            - the RF inputs are not BW limited  - can work in subsampling mode up to 400 MHz+ (depends on RF input transformers BW)

- 1x 14b D/A - 0...60 MHz RF (fNyq) output

            - LVDS connection

            - the RF output is not BW limited

- 2x USB2 on ARM

- 1x USB3 on FPGA

- 7 series FPGA, BGA 484, XC7A35T (or 50T, or maybe 75T or 100T also)

- Allwinner T113-S3 dual core 1.2 GHz ARM

            - CPU clock from FPGA - LVDS connection

- 7'' TFT, 16b

            - up to 50 MHz+ CLK (tested)

- 12 Layer PCB, controlled impedance

- I2S, SPI, IO connections between FPGA and ARM

- TLV320 audio codec

             - Stereo HPHONE and LINE output

- 2W audio PA

- ESD and RF protected audio line outputs (into codec)

- ESD and RF protected Optical Encoder input (for tuning)

- ESD protected and Opto-coupled input for CW key 

- ESD and overcurrent protected I/Os, USART, SPI, I2C on connectors

- SYNC signal output for DCDC power supply module  - LVDS connection on SATA connector

- USART debug port

- Differentially decoupled and Synchronized power supply on separate PCB

- Dedicated for HF SDR or for measurement tools

- Very high SNR and SFDR performance

- SDR FW development in progress

         
        - @NOTE The Fs of baseband i/q signal is 96 kHz -  2x 96 kHz slot used for two DDC channel

- implemented on FPGA side:

    - two independent DDC running in parallel at 122.88 MHz 

        - the 2x 16b signals from two ADC running in parallel and synced to one output clock of ADCs  

    - SUMming baseband channels with phase shift and magnitude scale (cordic level)          

    - I2S communication protocol

    - SPI communication protocol

    - 24 MHz clock output from PLL to ARM - LVDS output

- implemented on ARM side:

    - I2S communication protocol to FPGA  - (2x 96 kHz slot used for two DDC channel)

    - SPI communication protocol to FPGA 

    - two CIC freq. compensation filter
    - two Waterfall and Spectrum plot (A/B) at a time 
    - two Baseband Channel processed at a time
    - NR - high performance noise reduction

    - user graphics

- See some tests at the end of this page (uploads in progress)

- RFDSP board schematic

- PWR Supply schematic

 2026.06

The XtremeDx firmware V1.0 is nearly finished.

                                                       2023-05-02 -  PCB development DONE

                                        2x USB2, USB3 connections and FPGA, CPU capacitors

One layer from 4 high speed layers.

                                                            Bottom side copper and silks

                                                            Top side copper and silks

Mixed view of one high speed layer and top layer + silkscreen

2023-05-13 

Synchronized PWR SUPPLY

for RFDSP board and TFT display

(not a real size)

2023-08-23

XDX and XDX PWR PCBs

XDX RFDSP assembled - 2023

XDX PWR supply - assembly in progress

2024-03-14

PWR supply done

Testing the FPGA and the input/output clocks of the A/Ds  - LED blink

Testing the RF input relay

    

                                

First tests - under development  

 

20260615

Automatic Noise Canceller Test

(tested with two DDC channel)