Idiotizmus, szakmaitlanság, kóklerség

"Egészen elképesztő", hogy néhány HR-es idiótán, kókleren múlik sok mérnök szakmai fejlődése és megélhetése. Eppen most mondtad el az inter(júh)n , hogy beágyazott területen SoC bare-metal programozással is foglalkozol, erre megkérdezi, hogy: "és mikrovezérlőkkel is dolgozott?" 

A CV-t nem ildomos elolvasni két kávézás között. Az egy dolog, hogy a szakmai CV-ből a HR-esek nagyrésze semmit nem ért, de el sem olvassa.

Fáj a nájn, azt kész van.
Hova süllyedt a rádióamatőrködés is, „egészen elképesztő”. Röviden csak ez jut eszembe: „nem kell hozzá művészet, csak hangerő”, vagyis kevés kivételtől eltekintve a tudás már kihalt, szakmaiatlanná vált az egész.

XtremeDx H7113R Direct Conversion Transceiver

Project Overview

• Architecture: FPGA + SoC-based SDR Transceiver.
• Processor: Dual-core ARM Cortex-A7 (1.2 GHz) dedicated to DSP and GUI handling.
• Receiver: Dual-channel coherent RF/DDC receiver with hardware-level phasing-add implementation inside the FPGA.
• Interference Mitigation: CNLMS-based I/Q adaptive noise canceling.
• AF EQ: separate 8-band EQ for Rx and Tx AF signals
• RX RF Routing: Two completely independent RX RF routing blocks, each integrating:
  • Switchable 20 dB RF preamplifier.
  • Switchable RF 0.5 dB step attenuator.
  • Switchable High-Pass Filter (HPF).
  • Switchable direct ADC access via rear-panel SMA connectors (enabling subsampling and custom RF front-end modes).
• Antenna: Dual antenna inputs mapped to the phasing-add matrix inside FPGA and software-selectable RX and TX paths via the GUI menu.
• ADC: LTC2208 (16-bit, 122.88 MSPS) utilizing LVDS interface.
• DAC: TxDAC (14-bit, 122.88 MSPS) utilizing LVDS interface.
• RF Power Output: 120–140W PEP with 36–38 dB PEP IMD3 linearity across HF + 50 MHz bands.
• Connectivity:
  • USB 3.0 interface for direct high-speed FPGA-to-PC streaming.
  • USB 2.0 interface for ARM-to-PC communication.
  • Microphone (MIC) input with integrated MIC preamplifier.
  • AF line out & headphone output.
  • Dedicated CW key input.
• Display: 7" TFT panel with a 70 fps refresh rate.

Key Technical Highlights 

An FPGA + ARM SoC-based SDR transceiver featuring a dual-core 1.2 GHz Cortex-A7 processor dedicated to DSP and GUI management. 

The dual-channel coherent RF/DDC receiver utilizes hardware-accelerated phasing-add inside the FPGA. Features CNLMS-based I/Q adaptive filtering for advanced interference mitigation. 

RF conversion relies on an LVDS-connected 16-bit LTC2208 ADC and a 14-bit TxDAC, both operating at 122.88 MHz. 

For connectivity, the system integrates a USB 2.0 link for ARM-to-PC communication and a high-bandwidth USB 3.0 link for direct FPGA-to-PC data streaming. 

The RF power amplifier delivers 120–140W PEP with a highly linear 36–38 dB PEP IMD3 rating across the HF and 50 MHz bands. 

Visual monitoring provided by a 7" TFT display running at 70 fps.

Hardware related details:

The RF/DSP board

Rx RF Router

140W PEP - RF power amplifier

Transceiver assembly

Red based Visual Theme - 3D spectrum plot

Blue based Visual Theme - 3D spectrum plot

\Red based Visual Theme - 2D spectrum plot - two Rx Channel View

Red based Visual Theme - 2D spectrum plot - one Rx Channel View

Red based Visual Theme - 3D spectrum plot - one Rx Channel View - Polar plot for Phasing ADD mode - magnitude scale and phase rotating per Rx Channel 

Green based Visual Theme - 3D spectrum plot - one Rx Channel View

Green based Visual Theme - 3D spectrum plot - one Rx Channel View - polar plot for ANC (automatic noise cancelling) mode with CNLMS - magnitude scaling and phase rotating possibilities per Rx Channel 

Green based Visual Theme - 3D spectrum plot - two Rx Channel View - Main Menu View

Green based Visual Theme - 3D spectrum plot - two Rx Channel View

Tx 8 band EQ

Videos

ANC test using the same signal on RF inputs

XtremeDx K160-1 RF Sampler Board

XtremeDx K160-1 RF Sampler Board - Dedicated for HF beamforming

- PCB - 16L, controlled impedance

- FPGA - Kintex 7 - K160 / K325 / K410 

- A/D - 4x 130 / 160 MSPS, 16b  - LTC2208 /  LTC2209 - LVDS connection

- D/A 1x 2 channel 500 MSPS, 14b - LVDS connection

- High speed connections - PCIe 3 x4, SFP, 2x USB3 (connected to MGT, and via FTDI FT601), 2x SATA, MIPI DPHY (output),

 - I/O CON { I2S, SPI (LVDS connections), GPIOs }, 2x PLL - LVDS out for processor board sync 

- System Clock - used for A/D and D/A and can be used for onboard synthesizer reference clock 

- Clock Synthesizer - used for D/A and for PCIe/SFP/(MGT) reference clock

- External System Clock input - U.FL connector - connected to Clock Distributor - for multiple board synchronization

- Sync'd PWR supply on separate board (not showed)

PCB Bottom side

PCB TOP side

PCB TOP side

    One HS signal layer 

                                                             A/D / D/A clocks and MIPI OUT 

SOM module - 4-core ARM Cortex A53

- 4x 1.5 GHz ARM Cortex A53 core

- 2 - 4 GB LPDDR4

- eMMC, NOR FLASH

- High Speed Hirose Connectors

        - MCSI, NCSI, HDMI, LVDS display, 2x I2S, I2Cs, SPI ,...

- Sync power supply and high DCDC noise reduction (for SDR applications)

- 4x USB2 

 PCB development in progress.

XtremeDx SDR - USB3/FT601 interface implementation

Implementation of USB3.0 Super-Speed 32 bits Sync FIFO interface 

- device connected

- 1V8 I/O voltage, 67 MHz bus CLK 

- written interface code in VHDL

- interface simulation using a few data bytes

- the loopback test is working with 1kB data

- PC app - FT601 loopback demo app

Zoomed

FT601 interface VHDL code - part 1 - the concept

XtremeDx H7113R Transceiver - back side PCB and plate

HF Tx router

I2C controlled HF Tx router 

- 50 MHz Nyq filter

- Tx preamplifier

- preamplifier BIAS on/off by i2c

- direct signal routing on/off by i2c

- fixed value ATT on preamplifier in/out

- DC blocking and ESD protection at input