uprog research

2024. június 22., szombat

HF PA100 F101 2V0

HF PA100 F101 2V0

HF power amplifier 3.5...50 MHz

- output power: 120W..150W PEP from 50 MHz down to 3.5 MHz (150W PEP on 14.2 MHz)

- with driver section

- input power: 0..3 dBm

- min 30 dB PEP IMD3, max 36...38 dB PEP IMD3

2026.07 - 2V0

2024. január 10., szerda

Two element delta-loop antenna for 20m band

Two element critical coupled delta-loop antenna for 20m band.

The distance between elements is 3m. One element is radiator the another is the reflector. The radiation direction can be changed using relay.

The F/B ratio is 26..30 dB. The SWR is 1.2- 1.4.

2023. augusztus 23., szerda

QRO - Linear Power Tube Amplifier - 800W PEP CW/SSB

2x GI7B tubes.

2023. március 24., péntek

2023. január 29., vasárnap

XtremeDX HF SDR

- 2x 16b A/D (LTC2208) - 0...60 MHz RF (fNyq) input

- LVDS connection

- the RF inputs are not BW limited - can work in subsampling mode up to 400 MHz+ (depends on RF input transformers BW)

- 1x 14b D/A - 0...60 MHz RF (fNyq) output

- LVDS connection

- the RF output is not BW limited

- 2x USB2 on ARM

- 1x USB3 on FPGA

- 7 series FPGA, BGA 484, XC7A35T (or 50T, or maybe 75T or 100T also)

- Allwinner T113-S3 dual core 1.2 GHz ARM

- CPU clock from FPGA - LVDS connection

- 7'' TFT, 16b

- up to 50 MHz+ CLK (tested)

- 12 Layer PCB, controlled impedance

- I2S, SPI, IO connections between FPGA and ARM

- TLV320 audio codec

- Stereo HPHONE and LINE output

- 2W audio PA

- ESD and RF protected audio line outputs (into codec)

- ESD and RF protected Optical Encoder input (for tuning)

- ESD protected and Opto-coupled input for CW key

- ESD and overcurrent protected I/Os, USART, SPI, I2C on connectors

- SYNC signal output for DCDC power supply module - LVDS connection on SATA connector

- USART debug port

- Differentially decoupled and Synchronized power supply on separate PCB

- Dedicated for HF SDR or for measurement tools

- Very high SNR and SFDR performance

- SDR FW development in progress

- @NOTE The Fs of baseband i/q signal is 96 kHz - 2x 96 kHz slot used for two DDC channel

- implemented on FPGA side:

- two independent DDC running in parallel at 122.88 MHz

- the 2x 16b signals from two ADC running in parallel and synced to one output clock of ADCs

- SUMming baseband channels with phase shift and magnitude scale (cordic level)

- I2S communication protocol

- SPI communication protocol

- 24 MHz clock output from PLL to ARM - LVDS output

- implemented on ARM side:

- I2S communication protocol to FPGA - (2x 96 kHz slot used for two DDC channel)

- SPI communication protocol to FPGA

   - two CIC freq. compensation filter
   - two Waterfall and Spectrum plot (A/B) at a time
   - two Baseband Channel processed at a time
   - NR - high performance noise reduction

- user graphics

- See some tests at the end of this page (uploads in progress)

- RFDSP board schematic

- PWR Supply schematic

2026.06

The XtremeDx firmware V1.0 is nearly finished.

2023-05-02 - PCB development DONE

2x USB2, USB3 connections and FPGA, CPU capacitors

One layer from 4 high speed layers.

Bottom side copper and silks

Top side copper and silks

Mixed view of one high speed layer and top layer + silkscreen

2023-05-13

Synchronized PWR SUPPLY

for RFDSP board and TFT display

(not a real size)

2023-08-23

XDX and XDX PWR PCBs

XDX RFDSP assembled - 2023

XDX PWR supply - assembly in progress

2024-03-14

PWR supply done

Testing the FPGA and the input/output clocks of the A/Ds - LED blink

Testing the RF input relay

First tests - under development

20260615

Automatic Noise Canceller Test

(tested with two DDC channel)

2018. január 15., hétfő

Cort A5 basszusgitar tuningolas

Folyamatban, Cort A5 Woodhead hangszedokkel [ PU ]

2018. január 4., csütörtök

FPGA / ARM DSP radio

The beginning 2017.m.d
RFDSP board dev. done 2018.01.04

[ High speed RF-DSP board ]

122 MSPS AD & DA,
Altera Cyclone IV FPGA,
STM32 ARM,
TI Audio CODEC,
5'' TFT

FW: I/Q based demodulation, signal processing in freq. domain.

H7R HF SSB radio DSP board 1v0

02.12

2018.04.dd

2018.05.dd
Spread spectrum DCDC 12V IN, 3V3 5V 48V OUT

VHDL CIC [ DEC by 10 ] simulation

Spread Spectrum DCDC power source

2019.06.19

Első tesztek / First tests ~ 14.2 MHz.SSB / USB

2019.06.23

2019.07.15

2019.09.30

2019.10.27 CyanBlue skin. 7MHz.

2020-2021. ------------------------------------------------------------------------------------------------------------

H7R HF SSB radio 1v1 DSP board assembly in progress

New / modified DCDC PWR supply

H7R HF SSB radio 1v1 DSP board & the new power supply assembled, FW modified

RF router,
RX/TX preamps, HP and RX/TX NYQ filters, A/D & D/A direct connect - work in progress

TX / RF spectrum measurements
TX DAC is working

2022.07.dd

MIC input / PTT input RF blocking & ESD protection

- i2c controlled audio compressor and RF blocking - PCB design done

PA driver & HF PA100 W

- 100W PA in progress

100W HF PA & PA driver test

The PA input power is aprox. 0.7W, the output power is 100..120W. Tested from 3.5 MHz to 30 MHz.

The PA output Power will be aprox. 160..180W with 1,4..1,5 W input Power (modified PA driver development in progress).

New PA driver and improved IMD

PA100W driver with RD15HVF. BIAS current thermal stability. BIAS On / Off on PTT. The output power is 26 dBm (the sum of spectrum power measured with dual tone), That's enough to drive the PA100W. The IMD performance is 60 dBc IM3.

100W PA with 2x MRF101 DMOS. Improved IMD performance, 30 dBc IM3, the IM5 and others are below. The output power is 100..130 W PEP with SSB. Improved BIAS current thermal stability.

- 3.65 MHz - 90W PEP @ 30 dBc IM3

- 7.15 MHz - 90W PEP @ 30 dBc IM3

- 14.2 MHz - 130W PEP @ 30 dBc IM3

- 21.2 MHz - 110W PEP @ 30 dBc IM3

- 24.9 MHz - 90W PEP @ 30 dBc IM3

- 29.9 MHz - 80W PEP @ 30 dBc IM3