XtremeDx SDR - USB3/FT601 interface implementation

Implementation of USB3.0 Super-Speed 32 bits Sync FIFO interface 

- device connected

- 1V8 I/O voltage, 67 MHz bus CLK 

- written interface code in VHDL

- interface simulation using a few data bytes

- the loopback test is working with 1kB data

- PC app - FT601 loopback demo app

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FT601 interface VHDL code - part 1 - the concept